1. Field of the Invention
The present invention relates generally to package structures and fabrication methods thereof, and more particularly, to a QFN (Quad Flat Non-leaded) semiconductor package having electrical connecting structures and a fabrication method thereof.
2. Description of Related Art
Conventionally, a lead frame is used as a chip carrier for carrying a chip so as to form a semiconductor package. The lead frame essentially comprises a die pad and a plurality of leads formed at the periphery of the die pad. A chip is adhered to the die pad and electrically connected to the leads through a plurality of bonding wires. The chip, the die pad, the bonding wires and inner sections of the leads are then encapsulated by a packaging resin so as to form a semiconductor package having a lead frame.
Developing high integration and high density package structures has become a goal of semiconductor industries. Carriers for chip scale packages generally comprise lead frames, flexible substrates, rigid substrates and so on. Therein, lead frames are widely used in chip scale packages in electronic products due to their low costs and ease in processing. For example, a QFN (Quad Flat Non-leaded) package is a lead frame based chip scale package, which is characterized in that the leads thereof do not extend out from the package sides, thus reducing the overall package size.
FIG. 1A is a sectional view of a QFN package using a lead frame as a chip carrier as disclosed by U.S. Pat. Nos. 6,143,981, 6,130,115 and 6,198,171. Referring to FIG. 1A, a chip 12 is disposed on a lead frame 10 and electrically connected to leads 11 of the lead frame 10 through bonding wires 13, and an encapsulant 14 is formed to encasuplate the lead frame 10, the chip 12 and the bonding wires 13, wherein the bottom surfaces of the lead frame 10 and the leads 11 are exposed from the encapsulant 14 for mounting and electrically connecting an external device such as a printed circuit board through a solder material (not shown).
However, as shown in FIG. 1B, since the exposed surfaces of the leads 11 are flush with the encapsulant 14, when solder balls are mounted on the leads 11 for electrically connecting an external printed circuit board, solder bridge is likely to be formed between adjacent solder balls, thereby resulting in poor electrical connection between the package and the printed circuit board.
FIGS. 2A to 2D show a method for fabricating a QFN package without a carrier as disclosed by U.S. Pat. No. 5,830,800 and No. 6,498,099.
As shown in FIG. 2A, a plurality of electroplated projections 21 is formed on a copper plate 20 by electroplating.
As shown in FIG. 2B, a chip 22 is mounted on the electroplated projections 21 and electrically connected therewith through gold wires 23. Then, an encapsulant 24 is formed on the copper plate 20 to encapsulate the electroplated projections 21, the chip 22 and the gold wires 23.
As shown in FIGS. 2C and 2D, the copper plate 20 is removed to expose the bottom surfaces of the electroplated projections 21 and the encapsulant 24 such that an antioxidiation coating 25 is applied to the bottom surfaces of the electroplated projections 21 and the encapsulant 24, the antioxidation coating 25 partially exposing the electroplated projections 21. Further, solder balls 26 are mounted on the electroplated projections 21.
However, as shown in FIG. 2E, due to different CTEs of the antioxidation coating 25 and the encapsulant 24, delamination is easy to occur to the interface between the antioxidation coating 25 and the encapsualnt 24. As such, moisture can easily permeate therebetween and thus causes electrical leakage of the electroplated projections 21, thereby adversely affecting the electrical performance of the package. Further, as shown in FIG. 2C, since the surfaces of the electroplated projections 21 are flush with the surface of the encapsulant 24, the surfaces of the electroplated projections 21 can easily be scratched during the fabrication process. Furthermore, a soldering process or thermal cycling in practical applications may cause permeation of solder material into the interface between the antioxidation coating 25 and the encapsulant 24, thus resulting in electrical leakage and even short circuit at the interface.
In addition, if the electroplated projections 21 are located far away from the chip 22, long gold wires 23 are required, which accordingly increases the fabrication cost.
Therefore, it is imperative to overcome the above drawbacks of the prior art.